stm32f1xx_hal_tim.h 120 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f1xx_hal_tim.h
  4. * @author MCD Application Team
  5. * @brief Header file of TIM HAL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * Copyright (c) 2016 STMicroelectronics.
  10. * All rights reserved.
  11. *
  12. * This software is licensed under terms that can be found in the LICENSE file
  13. * in the root directory of this software component.
  14. * If no LICENSE file comes with this software, it is provided AS-IS.
  15. *
  16. ******************************************************************************
  17. */
  18. /* Define to prevent recursive inclusion -------------------------------------*/
  19. #ifndef STM32F1xx_HAL_TIM_H
  20. #define STM32F1xx_HAL_TIM_H
  21. #ifdef __cplusplus
  22. extern "C" {
  23. #endif
  24. /* Includes ------------------------------------------------------------------*/
  25. #include "stm32f1xx_hal_def.h"
  26. /** @addtogroup STM32F1xx_HAL_Driver
  27. * @{
  28. */
  29. /** @addtogroup TIM
  30. * @{
  31. */
  32. /* Exported types ------------------------------------------------------------*/
  33. /** @defgroup TIM_Exported_Types TIM Exported Types
  34. * @{
  35. */
  36. /**
  37. * @brief TIM Time base Configuration Structure definition
  38. */
  39. typedef struct
  40. {
  41. uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
  42. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
  43. uint32_t CounterMode; /*!< Specifies the counter mode.
  44. This parameter can be a value of @ref TIM_Counter_Mode */
  45. uint32_t Period; /*!< Specifies the period value to be loaded into the active
  46. Auto-Reload Register at the next update event.
  47. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
  48. uint32_t ClockDivision; /*!< Specifies the clock division.
  49. This parameter can be a value of @ref TIM_ClockDivision */
  50. uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
  51. reaches zero, an update event is generated and counting restarts
  52. from the RCR value (N).
  53. This means in PWM mode that (N+1) corresponds to:
  54. - the number of PWM periods in edge-aligned mode
  55. - the number of half PWM period in center-aligned mode
  56. GP timers: this parameter must be a number between Min_Data = 0x00 and
  57. Max_Data = 0xFF.
  58. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
  59. Max_Data = 0xFFFF. */
  60. uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
  61. This parameter can be a value of @ref TIM_AutoReloadPreload */
  62. } TIM_Base_InitTypeDef;
  63. /**
  64. * @brief TIM Output Compare Configuration Structure definition
  65. */
  66. typedef struct
  67. {
  68. uint32_t OCMode; /*!< Specifies the TIM mode.
  69. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
  70. uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
  71. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
  72. uint32_t OCPolarity; /*!< Specifies the output polarity.
  73. This parameter can be a value of @ref TIM_Output_Compare_Polarity */
  74. uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
  75. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
  76. @note This parameter is valid only for timer instances supporting break feature. */
  77. uint32_t OCFastMode; /*!< Specifies the Fast mode state.
  78. This parameter can be a value of @ref TIM_Output_Fast_State
  79. @note This parameter is valid only in PWM1 and PWM2 mode. */
  80. uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
  81. This parameter can be a value of @ref TIM_Output_Compare_Idle_State
  82. @note This parameter is valid only for timer instances supporting break feature. */
  83. uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
  84. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
  85. @note This parameter is valid only for timer instances supporting break feature. */
  86. } TIM_OC_InitTypeDef;
  87. /**
  88. * @brief TIM One Pulse Mode Configuration Structure definition
  89. */
  90. typedef struct
  91. {
  92. uint32_t OCMode; /*!< Specifies the TIM mode.
  93. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
  94. uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
  95. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
  96. uint32_t OCPolarity; /*!< Specifies the output polarity.
  97. This parameter can be a value of @ref TIM_Output_Compare_Polarity */
  98. uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
  99. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
  100. @note This parameter is valid only for timer instances supporting break feature. */
  101. uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
  102. This parameter can be a value of @ref TIM_Output_Compare_Idle_State
  103. @note This parameter is valid only for timer instances supporting break feature. */
  104. uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
  105. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
  106. @note This parameter is valid only for timer instances supporting break feature. */
  107. uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
  108. This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  109. uint32_t ICSelection; /*!< Specifies the input.
  110. This parameter can be a value of @ref TIM_Input_Capture_Selection */
  111. uint32_t ICFilter; /*!< Specifies the input capture filter.
  112. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  113. } TIM_OnePulse_InitTypeDef;
  114. /**
  115. * @brief TIM Input Capture Configuration Structure definition
  116. */
  117. typedef struct
  118. {
  119. uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
  120. This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  121. uint32_t ICSelection; /*!< Specifies the input.
  122. This parameter can be a value of @ref TIM_Input_Capture_Selection */
  123. uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
  124. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
  125. uint32_t ICFilter; /*!< Specifies the input capture filter.
  126. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  127. } TIM_IC_InitTypeDef;
  128. /**
  129. * @brief TIM Encoder Configuration Structure definition
  130. */
  131. typedef struct
  132. {
  133. uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
  134. This parameter can be a value of @ref TIM_Encoder_Mode */
  135. uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
  136. This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
  137. uint32_t IC1Selection; /*!< Specifies the input.
  138. This parameter can be a value of @ref TIM_Input_Capture_Selection */
  139. uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
  140. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
  141. uint32_t IC1Filter; /*!< Specifies the input capture filter.
  142. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  143. uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
  144. This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
  145. uint32_t IC2Selection; /*!< Specifies the input.
  146. This parameter can be a value of @ref TIM_Input_Capture_Selection */
  147. uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
  148. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
  149. uint32_t IC2Filter; /*!< Specifies the input capture filter.
  150. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  151. } TIM_Encoder_InitTypeDef;
  152. /**
  153. * @brief Clock Configuration Handle Structure definition
  154. */
  155. typedef struct
  156. {
  157. uint32_t ClockSource; /*!< TIM clock sources
  158. This parameter can be a value of @ref TIM_Clock_Source */
  159. uint32_t ClockPolarity; /*!< TIM clock polarity
  160. This parameter can be a value of @ref TIM_Clock_Polarity */
  161. uint32_t ClockPrescaler; /*!< TIM clock prescaler
  162. This parameter can be a value of @ref TIM_Clock_Prescaler */
  163. uint32_t ClockFilter; /*!< TIM clock filter
  164. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  165. } TIM_ClockConfigTypeDef;
  166. /**
  167. * @brief TIM Clear Input Configuration Handle Structure definition
  168. */
  169. typedef struct
  170. {
  171. uint32_t ClearInputState; /*!< TIM clear Input state
  172. This parameter can be ENABLE or DISABLE */
  173. uint32_t ClearInputSource; /*!< TIM clear Input sources
  174. This parameter can be a value of @ref TIM_ClearInput_Source */
  175. uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
  176. This parameter can be a value of @ref TIM_ClearInput_Polarity */
  177. uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
  178. This parameter must be 0: When OCRef clear feature is used with ETR source,
  179. ETR prescaler must be off */
  180. uint32_t ClearInputFilter; /*!< TIM Clear Input filter
  181. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  182. } TIM_ClearInputConfigTypeDef;
  183. /**
  184. * @brief TIM Master configuration Structure definition
  185. */
  186. typedef struct
  187. {
  188. uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
  189. This parameter can be a value of @ref TIM_Master_Mode_Selection */
  190. uint32_t MasterSlaveMode; /*!< Master/slave mode selection
  191. This parameter can be a value of @ref TIM_Master_Slave_Mode
  192. @note When the Master/slave mode is enabled, the effect of
  193. an event on the trigger input (TRGI) is delayed to allow a
  194. perfect synchronization between the current timer and its
  195. slaves (through TRGO). It is not mandatory in case of timer
  196. synchronization mode. */
  197. } TIM_MasterConfigTypeDef;
  198. /**
  199. * @brief TIM Slave configuration Structure definition
  200. */
  201. typedef struct
  202. {
  203. uint32_t SlaveMode; /*!< Slave mode selection
  204. This parameter can be a value of @ref TIM_Slave_Mode */
  205. uint32_t InputTrigger; /*!< Input Trigger source
  206. This parameter can be a value of @ref TIM_Trigger_Selection */
  207. uint32_t TriggerPolarity; /*!< Input Trigger polarity
  208. This parameter can be a value of @ref TIM_Trigger_Polarity */
  209. uint32_t TriggerPrescaler; /*!< Input trigger prescaler
  210. This parameter can be a value of @ref TIM_Trigger_Prescaler */
  211. uint32_t TriggerFilter; /*!< Input trigger filter
  212. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  213. } TIM_SlaveConfigTypeDef;
  214. /**
  215. * @brief TIM Break input(s) and Dead time configuration Structure definition
  216. * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
  217. * filter and polarity.
  218. */
  219. typedef struct
  220. {
  221. uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
  222. uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
  223. uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
  224. uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
  225. uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
  226. uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
  227. uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  228. uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
  229. } TIM_BreakDeadTimeConfigTypeDef;
  230. /**
  231. * @brief HAL State structures definition
  232. */
  233. typedef enum
  234. {
  235. HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
  236. HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
  237. HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
  238. HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
  239. HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
  240. } HAL_TIM_StateTypeDef;
  241. /**
  242. * @brief TIM Channel States definition
  243. */
  244. typedef enum
  245. {
  246. HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
  247. HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
  248. HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
  249. } HAL_TIM_ChannelStateTypeDef;
  250. /**
  251. * @brief DMA Burst States definition
  252. */
  253. typedef enum
  254. {
  255. HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
  256. HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
  257. HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
  258. } HAL_TIM_DMABurstStateTypeDef;
  259. /**
  260. * @brief HAL Active channel structures definition
  261. */
  262. typedef enum
  263. {
  264. HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
  265. HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
  266. HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
  267. HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
  268. HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
  269. } HAL_TIM_ActiveChannel;
  270. /**
  271. * @brief TIM Time Base Handle Structure definition
  272. */
  273. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  274. typedef struct __TIM_HandleTypeDef
  275. #else
  276. typedef struct
  277. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  278. {
  279. TIM_TypeDef *Instance; /*!< Register base address */
  280. TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
  281. HAL_TIM_ActiveChannel Channel; /*!< Active channel */
  282. DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
  283. This array is accessed by a @ref DMA_Handle_index */
  284. HAL_LockTypeDef Lock; /*!< Locking object */
  285. __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
  286. __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */
  287. __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
  288. __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
  289. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  290. void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
  291. void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
  292. void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
  293. void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
  294. void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
  295. void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
  296. void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
  297. void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
  298. void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
  299. void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
  300. void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
  301. void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
  302. void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
  303. void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
  304. void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
  305. void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
  306. void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
  307. void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
  308. void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
  309. void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
  310. void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
  311. void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
  312. void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
  313. void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
  314. void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
  315. void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
  316. void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
  317. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  318. } TIM_HandleTypeDef;
  319. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  320. /**
  321. * @brief HAL TIM Callback ID enumeration definition
  322. */
  323. typedef enum
  324. {
  325. HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
  326. , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
  327. , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
  328. , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
  329. , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
  330. , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
  331. , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
  332. , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
  333. , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
  334. , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
  335. , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
  336. , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
  337. , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
  338. , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
  339. , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
  340. , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
  341. , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
  342. , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
  343. , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
  344. , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
  345. , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
  346. , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
  347. , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
  348. , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
  349. , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
  350. , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
  351. , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
  352. } HAL_TIM_CallbackIDTypeDef;
  353. /**
  354. * @brief HAL TIM Callback pointer definition
  355. */
  356. typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
  357. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  358. /**
  359. * @}
  360. */
  361. /* End of exported types -----------------------------------------------------*/
  362. /* Exported constants --------------------------------------------------------*/
  363. /** @defgroup TIM_Exported_Constants TIM Exported Constants
  364. * @{
  365. */
  366. /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
  367. * @{
  368. */
  369. #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
  370. #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
  371. /**
  372. * @}
  373. */
  374. /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
  375. * @{
  376. */
  377. #define TIM_DMABASE_CR1 0x00000000U
  378. #define TIM_DMABASE_CR2 0x00000001U
  379. #define TIM_DMABASE_SMCR 0x00000002U
  380. #define TIM_DMABASE_DIER 0x00000003U
  381. #define TIM_DMABASE_SR 0x00000004U
  382. #define TIM_DMABASE_EGR 0x00000005U
  383. #define TIM_DMABASE_CCMR1 0x00000006U
  384. #define TIM_DMABASE_CCMR2 0x00000007U
  385. #define TIM_DMABASE_CCER 0x00000008U
  386. #define TIM_DMABASE_CNT 0x00000009U
  387. #define TIM_DMABASE_PSC 0x0000000AU
  388. #define TIM_DMABASE_ARR 0x0000000BU
  389. #define TIM_DMABASE_RCR 0x0000000CU
  390. #define TIM_DMABASE_CCR1 0x0000000DU
  391. #define TIM_DMABASE_CCR2 0x0000000EU
  392. #define TIM_DMABASE_CCR3 0x0000000FU
  393. #define TIM_DMABASE_CCR4 0x00000010U
  394. #define TIM_DMABASE_BDTR 0x00000011U
  395. #define TIM_DMABASE_DCR 0x00000012U
  396. #define TIM_DMABASE_DMAR 0x00000013U
  397. /**
  398. * @}
  399. */
  400. /** @defgroup TIM_Event_Source TIM Event Source
  401. * @{
  402. */
  403. #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
  404. #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
  405. #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
  406. #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
  407. #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
  408. #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
  409. #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
  410. #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
  411. /**
  412. * @}
  413. */
  414. /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
  415. * @{
  416. */
  417. #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
  418. #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
  419. #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
  420. /**
  421. * @}
  422. */
  423. /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
  424. * @{
  425. */
  426. #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
  427. #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
  428. /**
  429. * @}
  430. */
  431. /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
  432. * @{
  433. */
  434. #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
  435. #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
  436. #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
  437. #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
  438. /**
  439. * @}
  440. */
  441. /** @defgroup TIM_Counter_Mode TIM Counter Mode
  442. * @{
  443. */
  444. #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
  445. #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
  446. #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
  447. #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
  448. #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
  449. /**
  450. * @}
  451. */
  452. /** @defgroup TIM_ClockDivision TIM Clock Division
  453. * @{
  454. */
  455. #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
  456. #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
  457. #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
  458. /**
  459. * @}
  460. */
  461. /** @defgroup TIM_Output_Compare_State TIM Output Compare State
  462. * @{
  463. */
  464. #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
  465. #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
  466. /**
  467. * @}
  468. */
  469. /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
  470. * @{
  471. */
  472. #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
  473. #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
  474. /**
  475. * @}
  476. */
  477. /** @defgroup TIM_Output_Fast_State TIM Output Fast State
  478. * @{
  479. */
  480. #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
  481. #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
  482. /**
  483. * @}
  484. */
  485. /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
  486. * @{
  487. */
  488. #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
  489. #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
  490. /**
  491. * @}
  492. */
  493. /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
  494. * @{
  495. */
  496. #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
  497. #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
  498. /**
  499. * @}
  500. */
  501. /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
  502. * @{
  503. */
  504. #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
  505. #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
  506. /**
  507. * @}
  508. */
  509. /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
  510. * @{
  511. */
  512. #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
  513. #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
  514. /**
  515. * @}
  516. */
  517. /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
  518. * @{
  519. */
  520. #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
  521. #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
  522. /**
  523. * @}
  524. */
  525. /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
  526. * @{
  527. */
  528. #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
  529. #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
  530. #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
  531. /**
  532. * @}
  533. */
  534. /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
  535. * @{
  536. */
  537. #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
  538. #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
  539. /**
  540. * @}
  541. */
  542. /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
  543. * @{
  544. */
  545. #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
  546. #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
  547. #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
  548. /**
  549. * @}
  550. */
  551. /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
  552. * @{
  553. */
  554. #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
  555. #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
  556. #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
  557. #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
  558. /**
  559. * @}
  560. */
  561. /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
  562. * @{
  563. */
  564. #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
  565. #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
  566. /**
  567. * @}
  568. */
  569. /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
  570. * @{
  571. */
  572. #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
  573. #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
  574. #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
  575. /**
  576. * @}
  577. */
  578. /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
  579. * @{
  580. */
  581. #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
  582. #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
  583. #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
  584. #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
  585. #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
  586. #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
  587. #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
  588. #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
  589. /**
  590. * @}
  591. */
  592. /** @defgroup TIM_Commutation_Source TIM Commutation Source
  593. * @{
  594. */
  595. #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
  596. #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
  597. /**
  598. * @}
  599. */
  600. /** @defgroup TIM_DMA_sources TIM DMA Sources
  601. * @{
  602. */
  603. #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
  604. #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
  605. #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
  606. #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
  607. #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
  608. #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
  609. #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
  610. /**
  611. * @}
  612. */
  613. /** @defgroup TIM_CC_DMA_Request CCx DMA request selection
  614. * @{
  615. */
  616. #define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */
  617. #define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
  618. /**
  619. * @}
  620. */
  621. /** @defgroup TIM_Flag_definition TIM Flag Definition
  622. * @{
  623. */
  624. #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
  625. #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
  626. #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
  627. #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
  628. #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
  629. #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
  630. #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
  631. #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
  632. #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
  633. #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
  634. #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
  635. #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
  636. /**
  637. * @}
  638. */
  639. /** @defgroup TIM_Channel TIM Channel
  640. * @{
  641. */
  642. #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
  643. #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
  644. #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
  645. #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
  646. #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
  647. /**
  648. * @}
  649. */
  650. /** @defgroup TIM_Clock_Source TIM Clock Source
  651. * @{
  652. */
  653. #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
  654. #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
  655. #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
  656. #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
  657. #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
  658. #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
  659. #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
  660. #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
  661. #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
  662. #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
  663. /**
  664. * @}
  665. */
  666. /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
  667. * @{
  668. */
  669. #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
  670. #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
  671. #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
  672. #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
  673. #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
  674. /**
  675. * @}
  676. */
  677. /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
  678. * @{
  679. */
  680. #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
  681. #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
  682. #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
  683. #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
  684. /**
  685. * @}
  686. */
  687. /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
  688. * @{
  689. */
  690. #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
  691. #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
  692. /**
  693. * @}
  694. */
  695. /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
  696. * @{
  697. */
  698. #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
  699. #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
  700. #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
  701. #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
  702. /**
  703. * @}
  704. */
  705. /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
  706. * @{
  707. */
  708. #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
  709. #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
  710. /**
  711. * @}
  712. */
  713. /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
  714. * @{
  715. */
  716. #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
  717. #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
  718. /**
  719. * @}
  720. */
  721. /** @defgroup TIM_Lock_level TIM Lock level
  722. * @{
  723. */
  724. #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
  725. #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
  726. #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
  727. #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
  728. /**
  729. * @}
  730. */
  731. /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
  732. * @{
  733. */
  734. #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
  735. #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
  736. /**
  737. * @}
  738. */
  739. /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
  740. * @{
  741. */
  742. #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
  743. #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
  744. /**
  745. * @}
  746. */
  747. /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
  748. * @{
  749. */
  750. #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
  751. #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
  752. /**
  753. * @}
  754. */
  755. /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
  756. * @{
  757. */
  758. #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
  759. #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
  760. #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
  761. #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
  762. #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
  763. #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
  764. #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
  765. #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
  766. /**
  767. * @}
  768. */
  769. /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
  770. * @{
  771. */
  772. #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
  773. #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
  774. /**
  775. * @}
  776. */
  777. /** @defgroup TIM_Slave_Mode TIM Slave mode
  778. * @{
  779. */
  780. #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
  781. #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
  782. #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
  783. #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
  784. #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
  785. /**
  786. * @}
  787. */
  788. /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
  789. * @{
  790. */
  791. #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
  792. #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
  793. #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
  794. #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
  795. #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
  796. #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
  797. #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
  798. #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
  799. /**
  800. * @}
  801. */
  802. /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
  803. * @{
  804. */
  805. #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
  806. #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
  807. #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
  808. #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
  809. #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
  810. #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
  811. #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
  812. #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
  813. #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
  814. /**
  815. * @}
  816. */
  817. /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
  818. * @{
  819. */
  820. #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
  821. #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
  822. #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
  823. #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
  824. #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
  825. /**
  826. * @}
  827. */
  828. /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
  829. * @{
  830. */
  831. #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
  832. #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
  833. #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
  834. #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
  835. /**
  836. * @}
  837. */
  838. /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
  839. * @{
  840. */
  841. #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
  842. #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
  843. /**
  844. * @}
  845. */
  846. /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
  847. * @{
  848. */
  849. #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
  850. #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  851. #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  852. #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  853. #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  854. #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  855. #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  856. #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  857. #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  858. #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  859. #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  860. #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  861. #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  862. #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  863. #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  864. #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  865. #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  866. #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
  867. /**
  868. * @}
  869. */
  870. /** @defgroup DMA_Handle_index TIM DMA Handle Index
  871. * @{
  872. */
  873. #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
  874. #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
  875. #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
  876. #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
  877. #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
  878. #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
  879. #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
  880. /**
  881. * @}
  882. */
  883. /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
  884. * @{
  885. */
  886. #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
  887. #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
  888. #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
  889. #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
  890. /**
  891. * @}
  892. */
  893. /**
  894. * @}
  895. */
  896. /* End of exported constants -------------------------------------------------*/
  897. /* Exported macros -----------------------------------------------------------*/
  898. /** @defgroup TIM_Exported_Macros TIM Exported Macros
  899. * @{
  900. */
  901. /** @brief Reset TIM handle state.
  902. * @param __HANDLE__ TIM handle.
  903. * @retval None
  904. */
  905. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  906. #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
  907. (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
  908. (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
  909. (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
  910. (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
  911. (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
  912. (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
  913. (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
  914. (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
  915. (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
  916. (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
  917. (__HANDLE__)->Base_MspInitCallback = NULL; \
  918. (__HANDLE__)->Base_MspDeInitCallback = NULL; \
  919. (__HANDLE__)->IC_MspInitCallback = NULL; \
  920. (__HANDLE__)->IC_MspDeInitCallback = NULL; \
  921. (__HANDLE__)->OC_MspInitCallback = NULL; \
  922. (__HANDLE__)->OC_MspDeInitCallback = NULL; \
  923. (__HANDLE__)->PWM_MspInitCallback = NULL; \
  924. (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
  925. (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
  926. (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
  927. (__HANDLE__)->Encoder_MspInitCallback = NULL; \
  928. (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
  929. (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
  930. (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
  931. } while(0)
  932. #else
  933. #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
  934. (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
  935. (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
  936. (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
  937. (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
  938. (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
  939. (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
  940. (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
  941. (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
  942. (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
  943. (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
  944. } while(0)
  945. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  946. /**
  947. * @brief Enable the TIM peripheral.
  948. * @param __HANDLE__ TIM handle
  949. * @retval None
  950. */
  951. #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
  952. /**
  953. * @brief Enable the TIM main Output.
  954. * @param __HANDLE__ TIM handle
  955. * @retval None
  956. */
  957. #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
  958. /**
  959. * @brief Disable the TIM peripheral.
  960. * @param __HANDLE__ TIM handle
  961. * @retval None
  962. */
  963. #define __HAL_TIM_DISABLE(__HANDLE__) \
  964. do { \
  965. if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
  966. { \
  967. if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
  968. { \
  969. (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
  970. } \
  971. } \
  972. } while(0)
  973. /**
  974. * @brief Disable the TIM main Output.
  975. * @param __HANDLE__ TIM handle
  976. * @retval None
  977. * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
  978. * disabled
  979. */
  980. #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
  981. do { \
  982. if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
  983. { \
  984. if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
  985. { \
  986. (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
  987. } \
  988. } \
  989. } while(0)
  990. /**
  991. * @brief Disable the TIM main Output.
  992. * @param __HANDLE__ TIM handle
  993. * @retval None
  994. * @note The Main Output Enable of a timer instance is disabled unconditionally
  995. */
  996. #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
  997. /** @brief Enable the specified TIM interrupt.
  998. * @param __HANDLE__ specifies the TIM Handle.
  999. * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
  1000. * This parameter can be one of the following values:
  1001. * @arg TIM_IT_UPDATE: Update interrupt
  1002. * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
  1003. * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
  1004. * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
  1005. * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
  1006. * @arg TIM_IT_COM: Commutation interrupt
  1007. * @arg TIM_IT_TRIGGER: Trigger interrupt
  1008. * @arg TIM_IT_BREAK: Break interrupt
  1009. * @retval None
  1010. */
  1011. #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
  1012. /** @brief Disable the specified TIM interrupt.
  1013. * @param __HANDLE__ specifies the TIM Handle.
  1014. * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
  1015. * This parameter can be one of the following values:
  1016. * @arg TIM_IT_UPDATE: Update interrupt
  1017. * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
  1018. * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
  1019. * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
  1020. * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
  1021. * @arg TIM_IT_COM: Commutation interrupt
  1022. * @arg TIM_IT_TRIGGER: Trigger interrupt
  1023. * @arg TIM_IT_BREAK: Break interrupt
  1024. * @retval None
  1025. */
  1026. #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
  1027. /** @brief Enable the specified DMA request.
  1028. * @param __HANDLE__ specifies the TIM Handle.
  1029. * @param __DMA__ specifies the TIM DMA request to enable.
  1030. * This parameter can be one of the following values:
  1031. * @arg TIM_DMA_UPDATE: Update DMA request
  1032. * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
  1033. * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
  1034. * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
  1035. * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
  1036. * @arg TIM_DMA_COM: Commutation DMA request
  1037. * @arg TIM_DMA_TRIGGER: Trigger DMA request
  1038. * @retval None
  1039. */
  1040. #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
  1041. /** @brief Disable the specified DMA request.
  1042. * @param __HANDLE__ specifies the TIM Handle.
  1043. * @param __DMA__ specifies the TIM DMA request to disable.
  1044. * This parameter can be one of the following values:
  1045. * @arg TIM_DMA_UPDATE: Update DMA request
  1046. * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
  1047. * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
  1048. * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
  1049. * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
  1050. * @arg TIM_DMA_COM: Commutation DMA request
  1051. * @arg TIM_DMA_TRIGGER: Trigger DMA request
  1052. * @retval None
  1053. */
  1054. #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
  1055. /** @brief Check whether the specified TIM interrupt flag is set or not.
  1056. * @param __HANDLE__ specifies the TIM Handle.
  1057. * @param __FLAG__ specifies the TIM interrupt flag to check.
  1058. * This parameter can be one of the following values:
  1059. * @arg TIM_FLAG_UPDATE: Update interrupt flag
  1060. * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  1061. * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  1062. * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  1063. * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  1064. * @arg TIM_FLAG_COM: Commutation interrupt flag
  1065. * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
  1066. * @arg TIM_FLAG_BREAK: Break interrupt flag
  1067. * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  1068. * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  1069. * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  1070. * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
  1071. * @retval The new state of __FLAG__ (TRUE or FALSE).
  1072. */
  1073. #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
  1074. /** @brief Clear the specified TIM interrupt flag.
  1075. * @param __HANDLE__ specifies the TIM Handle.
  1076. * @param __FLAG__ specifies the TIM interrupt flag to clear.
  1077. * This parameter can be one of the following values:
  1078. * @arg TIM_FLAG_UPDATE: Update interrupt flag
  1079. * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  1080. * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  1081. * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  1082. * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  1083. * @arg TIM_FLAG_COM: Commutation interrupt flag
  1084. * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
  1085. * @arg TIM_FLAG_BREAK: Break interrupt flag
  1086. * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  1087. * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  1088. * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  1089. * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
  1090. * @retval The new state of __FLAG__ (TRUE or FALSE).
  1091. */
  1092. #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
  1093. /**
  1094. * @brief Check whether the specified TIM interrupt source is enabled or not.
  1095. * @param __HANDLE__ TIM handle
  1096. * @param __INTERRUPT__ specifies the TIM interrupt source to check.
  1097. * This parameter can be one of the following values:
  1098. * @arg TIM_IT_UPDATE: Update interrupt
  1099. * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
  1100. * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
  1101. * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
  1102. * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
  1103. * @arg TIM_IT_COM: Commutation interrupt
  1104. * @arg TIM_IT_TRIGGER: Trigger interrupt
  1105. * @arg TIM_IT_BREAK: Break interrupt
  1106. * @retval The state of TIM_IT (SET or RESET).
  1107. */
  1108. #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
  1109. == (__INTERRUPT__)) ? SET : RESET)
  1110. /** @brief Clear the TIM interrupt pending bits.
  1111. * @param __HANDLE__ TIM handle
  1112. * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
  1113. * This parameter can be one of the following values:
  1114. * @arg TIM_IT_UPDATE: Update interrupt
  1115. * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
  1116. * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
  1117. * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
  1118. * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
  1119. * @arg TIM_IT_COM: Commutation interrupt
  1120. * @arg TIM_IT_TRIGGER: Trigger interrupt
  1121. * @arg TIM_IT_BREAK: Break interrupt
  1122. * @retval None
  1123. */
  1124. #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
  1125. /**
  1126. * @brief Indicates whether or not the TIM Counter is used as downcounter.
  1127. * @param __HANDLE__ TIM handle.
  1128. * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
  1129. * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
  1130. * or Encoder mode.
  1131. */
  1132. #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
  1133. /**
  1134. * @brief Set the TIM Prescaler on runtime.
  1135. * @param __HANDLE__ TIM handle.
  1136. * @param __PRESC__ specifies the Prescaler new value.
  1137. * @retval None
  1138. */
  1139. #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
  1140. /**
  1141. * @brief Set the TIM Counter Register value on runtime.
  1142. * @param __HANDLE__ TIM handle.
  1143. * @param __COUNTER__ specifies the Counter register new value.
  1144. * @retval None
  1145. */
  1146. #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
  1147. /**
  1148. * @brief Get the TIM Counter Register value on runtime.
  1149. * @param __HANDLE__ TIM handle.
  1150. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
  1151. */
  1152. #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
  1153. /**
  1154. * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
  1155. * @param __HANDLE__ TIM handle.
  1156. * @param __AUTORELOAD__ specifies the Counter register new value.
  1157. * @retval None
  1158. */
  1159. #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
  1160. do{ \
  1161. (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
  1162. (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
  1163. } while(0)
  1164. /**
  1165. * @brief Get the TIM Autoreload Register value on runtime.
  1166. * @param __HANDLE__ TIM handle.
  1167. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
  1168. */
  1169. #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
  1170. /**
  1171. * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
  1172. * @param __HANDLE__ TIM handle.
  1173. * @param __CKD__ specifies the clock division value.
  1174. * This parameter can be one of the following value:
  1175. * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  1176. * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  1177. * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
  1178. * @retval None
  1179. */
  1180. #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
  1181. do{ \
  1182. (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
  1183. (__HANDLE__)->Instance->CR1 |= (__CKD__); \
  1184. (__HANDLE__)->Init.ClockDivision = (__CKD__); \
  1185. } while(0)
  1186. /**
  1187. * @brief Get the TIM Clock Division value on runtime.
  1188. * @param __HANDLE__ TIM handle.
  1189. * @retval The clock division can be one of the following values:
  1190. * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  1191. * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  1192. * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
  1193. */
  1194. #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
  1195. /**
  1196. * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
  1197. * function.
  1198. * @param __HANDLE__ TIM handle.
  1199. * @param __CHANNEL__ TIM Channels to be configured.
  1200. * This parameter can be one of the following values:
  1201. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1202. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1203. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1204. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1205. * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
  1206. * This parameter can be one of the following values:
  1207. * @arg TIM_ICPSC_DIV1: no prescaler
  1208. * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
  1209. * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
  1210. * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
  1211. * @retval None
  1212. */
  1213. #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
  1214. do{ \
  1215. TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
  1216. TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
  1217. } while(0)
  1218. /**
  1219. * @brief Get the TIM Input Capture prescaler on runtime.
  1220. * @param __HANDLE__ TIM handle.
  1221. * @param __CHANNEL__ TIM Channels to be configured.
  1222. * This parameter can be one of the following values:
  1223. * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
  1224. * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
  1225. * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
  1226. * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
  1227. * @retval The input capture prescaler can be one of the following values:
  1228. * @arg TIM_ICPSC_DIV1: no prescaler
  1229. * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
  1230. * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
  1231. * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
  1232. */
  1233. #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
  1234. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
  1235. ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
  1236. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
  1237. (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
  1238. /**
  1239. * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
  1240. * @param __HANDLE__ TIM handle.
  1241. * @param __CHANNEL__ TIM Channels to be configured.
  1242. * This parameter can be one of the following values:
  1243. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1244. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1245. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1246. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1247. * @param __COMPARE__ specifies the Capture Compare register new value.
  1248. * @retval None
  1249. */
  1250. #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
  1251. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
  1252. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
  1253. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
  1254. ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
  1255. /**
  1256. * @brief Get the TIM Capture Compare Register value on runtime.
  1257. * @param __HANDLE__ TIM handle.
  1258. * @param __CHANNEL__ TIM Channel associated with the capture compare register
  1259. * This parameter can be one of the following values:
  1260. * @arg TIM_CHANNEL_1: get capture/compare 1 register value
  1261. * @arg TIM_CHANNEL_2: get capture/compare 2 register value
  1262. * @arg TIM_CHANNEL_3: get capture/compare 3 register value
  1263. * @arg TIM_CHANNEL_4: get capture/compare 4 register value
  1264. * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
  1265. */
  1266. #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
  1267. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
  1268. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
  1269. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
  1270. ((__HANDLE__)->Instance->CCR4))
  1271. /**
  1272. * @brief Set the TIM Output compare preload.
  1273. * @param __HANDLE__ TIM handle.
  1274. * @param __CHANNEL__ TIM Channels to be configured.
  1275. * This parameter can be one of the following values:
  1276. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1277. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1278. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1279. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1280. * @retval None
  1281. */
  1282. #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
  1283. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
  1284. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
  1285. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
  1286. ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
  1287. /**
  1288. * @brief Reset the TIM Output compare preload.
  1289. * @param __HANDLE__ TIM handle.
  1290. * @param __CHANNEL__ TIM Channels to be configured.
  1291. * This parameter can be one of the following values:
  1292. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1293. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1294. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1295. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1296. * @retval None
  1297. */
  1298. #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
  1299. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
  1300. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
  1301. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
  1302. ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
  1303. /**
  1304. * @brief Enable fast mode for a given channel.
  1305. * @param __HANDLE__ TIM handle.
  1306. * @param __CHANNEL__ TIM Channels to be configured.
  1307. * This parameter can be one of the following values:
  1308. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1309. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1310. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1311. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1312. * @note When fast mode is enabled an active edge on the trigger input acts
  1313. * like a compare match on CCx output. Delay to sample the trigger
  1314. * input and to activate CCx output is reduced to 3 clock cycles.
  1315. * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
  1316. * @retval None
  1317. */
  1318. #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
  1319. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
  1320. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
  1321. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
  1322. ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
  1323. /**
  1324. * @brief Disable fast mode for a given channel.
  1325. * @param __HANDLE__ TIM handle.
  1326. * @param __CHANNEL__ TIM Channels to be configured.
  1327. * This parameter can be one of the following values:
  1328. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1329. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1330. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1331. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1332. * @note When fast mode is disabled CCx output behaves normally depending
  1333. * on counter and CCRx values even when the trigger is ON. The minimum
  1334. * delay to activate CCx output when an active edge occurs on the
  1335. * trigger input is 5 clock cycles.
  1336. * @retval None
  1337. */
  1338. #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
  1339. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
  1340. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
  1341. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
  1342. ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
  1343. /**
  1344. * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
  1345. * @param __HANDLE__ TIM handle.
  1346. * @note When the URS bit of the TIMx_CR1 register is set, only counter
  1347. * overflow/underflow generates an update interrupt or DMA request (if
  1348. * enabled)
  1349. * @retval None
  1350. */
  1351. #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
  1352. /**
  1353. * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
  1354. * @param __HANDLE__ TIM handle.
  1355. * @note When the URS bit of the TIMx_CR1 register is reset, any of the
  1356. * following events generate an update interrupt or DMA request (if
  1357. * enabled):
  1358. * _ Counter overflow underflow
  1359. * _ Setting the UG bit
  1360. * _ Update generation through the slave mode controller
  1361. * @retval None
  1362. */
  1363. #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
  1364. /**
  1365. * @brief Set the TIM Capture x input polarity on runtime.
  1366. * @param __HANDLE__ TIM handle.
  1367. * @param __CHANNEL__ TIM Channels to be configured.
  1368. * This parameter can be one of the following values:
  1369. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1370. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1371. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1372. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1373. * @param __POLARITY__ Polarity for TIx source
  1374. * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  1375. * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  1376. * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
  1377. * @retval None
  1378. */
  1379. #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
  1380. do{ \
  1381. TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
  1382. TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
  1383. }while(0)
  1384. /** @brief Select the Capture/compare DMA request source.
  1385. * @param __HANDLE__ specifies the TIM Handle.
  1386. * @param __CCDMA__ specifies Capture/compare DMA request source
  1387. * This parameter can be one of the following values:
  1388. * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
  1389. * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
  1390. * @retval None
  1391. */
  1392. #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \
  1393. MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
  1394. /**
  1395. * @}
  1396. */
  1397. /* End of exported macros ----------------------------------------------------*/
  1398. /* Private constants ---------------------------------------------------------*/
  1399. /** @defgroup TIM_Private_Constants TIM Private Constants
  1400. * @{
  1401. */
  1402. /* The counter of a timer instance is disabled only if all the CCx and CCxN
  1403. channels have been disabled */
  1404. #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
  1405. #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
  1406. /**
  1407. * @}
  1408. */
  1409. /* End of private constants --------------------------------------------------*/
  1410. /* Private macros ------------------------------------------------------------*/
  1411. /** @defgroup TIM_Private_Macros TIM Private Macros
  1412. * @{
  1413. */
  1414. #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
  1415. ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
  1416. #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
  1417. ((__BASE__) == TIM_DMABASE_CR2) || \
  1418. ((__BASE__) == TIM_DMABASE_SMCR) || \
  1419. ((__BASE__) == TIM_DMABASE_DIER) || \
  1420. ((__BASE__) == TIM_DMABASE_SR) || \
  1421. ((__BASE__) == TIM_DMABASE_EGR) || \
  1422. ((__BASE__) == TIM_DMABASE_CCMR1) || \
  1423. ((__BASE__) == TIM_DMABASE_CCMR2) || \
  1424. ((__BASE__) == TIM_DMABASE_CCER) || \
  1425. ((__BASE__) == TIM_DMABASE_CNT) || \
  1426. ((__BASE__) == TIM_DMABASE_PSC) || \
  1427. ((__BASE__) == TIM_DMABASE_ARR) || \
  1428. ((__BASE__) == TIM_DMABASE_RCR) || \
  1429. ((__BASE__) == TIM_DMABASE_CCR1) || \
  1430. ((__BASE__) == TIM_DMABASE_CCR2) || \
  1431. ((__BASE__) == TIM_DMABASE_CCR3) || \
  1432. ((__BASE__) == TIM_DMABASE_CCR4) || \
  1433. ((__BASE__) == TIM_DMABASE_BDTR))
  1434. #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
  1435. #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
  1436. ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
  1437. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
  1438. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
  1439. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
  1440. #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
  1441. ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
  1442. ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
  1443. #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
  1444. ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
  1445. #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
  1446. ((__STATE__) == TIM_OCFAST_ENABLE))
  1447. #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
  1448. ((__POLARITY__) == TIM_OCPOLARITY_LOW))
  1449. #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
  1450. ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
  1451. #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
  1452. ((__STATE__) == TIM_OCIDLESTATE_RESET))
  1453. #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
  1454. ((__STATE__) == TIM_OCNIDLESTATE_RESET))
  1455. #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
  1456. ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
  1457. #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
  1458. ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
  1459. ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
  1460. #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
  1461. ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
  1462. ((__SELECTION__) == TIM_ICSELECTION_TRC))
  1463. #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
  1464. ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
  1465. ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
  1466. ((__PRESCALER__) == TIM_ICPSC_DIV8))
  1467. #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
  1468. ((__MODE__) == TIM_OPMODE_REPETITIVE))
  1469. #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
  1470. ((__MODE__) == TIM_ENCODERMODE_TI2) || \
  1471. ((__MODE__) == TIM_ENCODERMODE_TI12))
  1472. #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
  1473. #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
  1474. ((__CHANNEL__) == TIM_CHANNEL_2) || \
  1475. ((__CHANNEL__) == TIM_CHANNEL_3) || \
  1476. ((__CHANNEL__) == TIM_CHANNEL_4) || \
  1477. ((__CHANNEL__) == TIM_CHANNEL_ALL))
  1478. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
  1479. ((__CHANNEL__) == TIM_CHANNEL_2))
  1480. #define IS_TIM_PERIOD(__PERIOD__) (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0xFFFFU))
  1481. #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
  1482. ((__CHANNEL__) == TIM_CHANNEL_2) || \
  1483. ((__CHANNEL__) == TIM_CHANNEL_3))
  1484. #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
  1485. ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
  1486. ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
  1487. ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
  1488. ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
  1489. ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
  1490. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
  1491. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
  1492. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
  1493. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
  1494. #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
  1495. ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
  1496. ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
  1497. ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
  1498. ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
  1499. #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
  1500. ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
  1501. ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
  1502. ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
  1503. #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
  1504. #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
  1505. ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
  1506. #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
  1507. ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
  1508. ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
  1509. ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
  1510. #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
  1511. #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
  1512. ((__STATE__) == TIM_OSSR_DISABLE))
  1513. #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
  1514. ((__STATE__) == TIM_OSSI_DISABLE))
  1515. #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
  1516. ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
  1517. ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
  1518. ((__LEVEL__) == TIM_LOCKLEVEL_3))
  1519. #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
  1520. #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
  1521. ((__STATE__) == TIM_BREAK_DISABLE))
  1522. #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
  1523. ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
  1524. #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
  1525. ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
  1526. #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
  1527. ((__SOURCE__) == TIM_TRGO_ENABLE) || \
  1528. ((__SOURCE__) == TIM_TRGO_UPDATE) || \
  1529. ((__SOURCE__) == TIM_TRGO_OC1) || \
  1530. ((__SOURCE__) == TIM_TRGO_OC1REF) || \
  1531. ((__SOURCE__) == TIM_TRGO_OC2REF) || \
  1532. ((__SOURCE__) == TIM_TRGO_OC3REF) || \
  1533. ((__SOURCE__) == TIM_TRGO_OC4REF))
  1534. #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
  1535. ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
  1536. #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
  1537. ((__MODE__) == TIM_SLAVEMODE_RESET) || \
  1538. ((__MODE__) == TIM_SLAVEMODE_GATED) || \
  1539. ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
  1540. ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
  1541. #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
  1542. ((__MODE__) == TIM_OCMODE_PWM2))
  1543. #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
  1544. ((__MODE__) == TIM_OCMODE_ACTIVE) || \
  1545. ((__MODE__) == TIM_OCMODE_INACTIVE) || \
  1546. ((__MODE__) == TIM_OCMODE_TOGGLE) || \
  1547. ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
  1548. ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
  1549. #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
  1550. ((__SELECTION__) == TIM_TS_ITR1) || \
  1551. ((__SELECTION__) == TIM_TS_ITR2) || \
  1552. ((__SELECTION__) == TIM_TS_ITR3) || \
  1553. ((__SELECTION__) == TIM_TS_TI1F_ED) || \
  1554. ((__SELECTION__) == TIM_TS_TI1FP1) || \
  1555. ((__SELECTION__) == TIM_TS_TI2FP2) || \
  1556. ((__SELECTION__) == TIM_TS_ETRF))
  1557. #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
  1558. ((__SELECTION__) == TIM_TS_ITR1) || \
  1559. ((__SELECTION__) == TIM_TS_ITR2) || \
  1560. ((__SELECTION__) == TIM_TS_ITR3) || \
  1561. ((__SELECTION__) == TIM_TS_NONE))
  1562. #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
  1563. ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
  1564. ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
  1565. ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
  1566. ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
  1567. #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
  1568. ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
  1569. ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
  1570. ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
  1571. #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
  1572. #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
  1573. ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
  1574. #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
  1575. ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
  1576. ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
  1577. ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
  1578. ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
  1579. ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
  1580. ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
  1581. ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
  1582. ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
  1583. ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
  1584. ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
  1585. ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
  1586. ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
  1587. ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
  1588. ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
  1589. ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
  1590. ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
  1591. ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
  1592. #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
  1593. #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
  1594. #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
  1595. #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
  1596. #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
  1597. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
  1598. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
  1599. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
  1600. ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
  1601. #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
  1602. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
  1603. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
  1604. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
  1605. ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
  1606. #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
  1607. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
  1608. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
  1609. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
  1610. ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
  1611. #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
  1612. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
  1613. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
  1614. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
  1615. ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
  1616. #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
  1617. (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
  1618. ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
  1619. ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
  1620. (__HANDLE__)->ChannelState[3])
  1621. #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
  1622. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
  1623. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
  1624. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
  1625. ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
  1626. #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
  1627. (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
  1628. (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
  1629. (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
  1630. (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
  1631. } while(0)
  1632. #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
  1633. (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
  1634. ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
  1635. ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
  1636. (__HANDLE__)->ChannelNState[3])
  1637. #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
  1638. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
  1639. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
  1640. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
  1641. ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
  1642. #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
  1643. (__HANDLE__)->ChannelNState[0] = \
  1644. (__CHANNEL_STATE__); \
  1645. (__HANDLE__)->ChannelNState[1] = \
  1646. (__CHANNEL_STATE__); \
  1647. (__HANDLE__)->ChannelNState[2] = \
  1648. (__CHANNEL_STATE__); \
  1649. (__HANDLE__)->ChannelNState[3] = \
  1650. (__CHANNEL_STATE__); \
  1651. } while(0)
  1652. /**
  1653. * @}
  1654. */
  1655. /* End of private macros -----------------------------------------------------*/
  1656. /* Include TIM HAL Extended module */
  1657. #include "stm32f1xx_hal_tim_ex.h"
  1658. /* Exported functions --------------------------------------------------------*/
  1659. /** @addtogroup TIM_Exported_Functions TIM Exported Functions
  1660. * @{
  1661. */
  1662. /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
  1663. * @brief Time Base functions
  1664. * @{
  1665. */
  1666. /* Time Base functions ********************************************************/
  1667. HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
  1668. HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
  1669. void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
  1670. void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
  1671. /* Blocking mode: Polling */
  1672. HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
  1673. HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
  1674. /* Non-Blocking mode: Interrupt */
  1675. HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
  1676. HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
  1677. /* Non-Blocking mode: DMA */
  1678. HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
  1679. HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
  1680. /**
  1681. * @}
  1682. */
  1683. /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
  1684. * @brief TIM Output Compare functions
  1685. * @{
  1686. */
  1687. /* Timer Output Compare functions *********************************************/
  1688. HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
  1689. HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
  1690. void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
  1691. void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
  1692. /* Blocking mode: Polling */
  1693. HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1694. HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1695. /* Non-Blocking mode: Interrupt */
  1696. HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1697. HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1698. /* Non-Blocking mode: DMA */
  1699. HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
  1700. uint16_t Length);
  1701. HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1702. /**
  1703. * @}
  1704. */
  1705. /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
  1706. * @brief TIM PWM functions
  1707. * @{
  1708. */
  1709. /* Timer PWM functions ********************************************************/
  1710. HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
  1711. HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
  1712. void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
  1713. void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
  1714. /* Blocking mode: Polling */
  1715. HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1716. HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1717. /* Non-Blocking mode: Interrupt */
  1718. HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1719. HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1720. /* Non-Blocking mode: DMA */
  1721. HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
  1722. uint16_t Length);
  1723. HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1724. /**
  1725. * @}
  1726. */
  1727. /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
  1728. * @brief TIM Input Capture functions
  1729. * @{
  1730. */
  1731. /* Timer Input Capture functions **********************************************/
  1732. HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
  1733. HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
  1734. void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
  1735. void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
  1736. /* Blocking mode: Polling */
  1737. HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1738. HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1739. /* Non-Blocking mode: Interrupt */
  1740. HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1741. HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1742. /* Non-Blocking mode: DMA */
  1743. HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
  1744. HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1745. /**
  1746. * @}
  1747. */
  1748. /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
  1749. * @brief TIM One Pulse functions
  1750. * @{
  1751. */
  1752. /* Timer One Pulse functions **************************************************/
  1753. HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
  1754. HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
  1755. void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
  1756. void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
  1757. /* Blocking mode: Polling */
  1758. HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1759. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1760. /* Non-Blocking mode: Interrupt */
  1761. HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1762. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1763. /**
  1764. * @}
  1765. */
  1766. /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
  1767. * @brief TIM Encoder functions
  1768. * @{
  1769. */
  1770. /* Timer Encoder functions ****************************************************/
  1771. HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
  1772. HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
  1773. void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
  1774. void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
  1775. /* Blocking mode: Polling */
  1776. HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1777. HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1778. /* Non-Blocking mode: Interrupt */
  1779. HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1780. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1781. /* Non-Blocking mode: DMA */
  1782. HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
  1783. uint32_t *pData2, uint16_t Length);
  1784. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1785. /**
  1786. * @}
  1787. */
  1788. /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
  1789. * @brief IRQ handler management
  1790. * @{
  1791. */
  1792. /* Interrupt Handler functions ***********************************************/
  1793. void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
  1794. /**
  1795. * @}
  1796. */
  1797. /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
  1798. * @brief Peripheral Control functions
  1799. * @{
  1800. */
  1801. /* Control functions *********************************************************/
  1802. HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
  1803. uint32_t Channel);
  1804. HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
  1805. uint32_t Channel);
  1806. HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
  1807. uint32_t Channel);
  1808. HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
  1809. uint32_t OutputChannel, uint32_t InputChannel);
  1810. HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
  1811. const TIM_ClearInputConfigTypeDef *sClearInputConfig,
  1812. uint32_t Channel);
  1813. HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
  1814. HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
  1815. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
  1816. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
  1817. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  1818. uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
  1819. HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  1820. uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
  1821. uint32_t BurstLength, uint32_t DataLength);
  1822. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
  1823. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  1824. uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
  1825. HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  1826. uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
  1827. uint32_t BurstLength, uint32_t DataLength);
  1828. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
  1829. HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
  1830. uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
  1831. /**
  1832. * @}
  1833. */
  1834. /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
  1835. * @brief TIM Callbacks functions
  1836. * @{
  1837. */
  1838. /* Callback in non blocking modes (Interrupt and DMA) *************************/
  1839. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
  1840. void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
  1841. void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
  1842. void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
  1843. void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
  1844. void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
  1845. void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
  1846. void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
  1847. void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
  1848. void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
  1849. /* Callbacks Register/UnRegister functions ***********************************/
  1850. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1851. HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
  1852. pTIM_CallbackTypeDef pCallback);
  1853. HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
  1854. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1855. /**
  1856. * @}
  1857. */
  1858. /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
  1859. * @brief Peripheral State functions
  1860. * @{
  1861. */
  1862. /* Peripheral State functions ************************************************/
  1863. HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
  1864. HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
  1865. HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
  1866. HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
  1867. HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
  1868. HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
  1869. /* Peripheral Channel state functions ************************************************/
  1870. HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
  1871. HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel);
  1872. HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
  1873. /**
  1874. * @}
  1875. */
  1876. /**
  1877. * @}
  1878. */
  1879. /* End of exported functions -------------------------------------------------*/
  1880. /* Private functions----------------------------------------------------------*/
  1881. /** @defgroup TIM_Private_Functions TIM Private Functions
  1882. * @{
  1883. */
  1884. void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
  1885. void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
  1886. void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
  1887. void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
  1888. uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
  1889. void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
  1890. void TIM_DMAError(DMA_HandleTypeDef *hdma);
  1891. void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
  1892. void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
  1893. void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
  1894. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1895. void TIM_ResetCallback(TIM_HandleTypeDef *htim);
  1896. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1897. /**
  1898. * @}
  1899. */
  1900. /* End of private functions --------------------------------------------------*/
  1901. /**
  1902. * @}
  1903. */
  1904. /**
  1905. * @}
  1906. */
  1907. #ifdef __cplusplus
  1908. }
  1909. #endif
  1910. #endif /* STM32F1xx_HAL_TIM_H */