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centralCtrSys_STM32F103ZE_1.0.0.dbgconf

centralCtrSys_STM32F103ZE_1.0.0.dbgconf 2.3 KB
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  1. // File: STM32F101_102_103_105_107.dbgconf
    2. 

  2. // Version: 1.0.0
    3. 

  3. // Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
    4. 

  4. //                STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
    5. 

  5. 

  6. // <<< Use Configuration Wizard in Context Menu >>>
    7. 

  7. 

  8. // <h> Debug MCU configuration register (DBGMCU_CR)
    9. 

  9. //                                   <i> Reserved bits must be kept at reset value
    10. 

  10. //   <o.30> DBG_TIM11_STOP           <i> TIM11 counter stopped when core is halted
    11. 

  11. //   <o.29> DBG_TIM10_STOP           <i> TIM10 counter stopped when core is halted
    12. 

  12. //   <o.28> DBG_TIM9_STOP            <i> TIM9 counter stopped when core is halted
    13. 

  13. //   <o.27> DBG_TIM14_STOP           <i> TIM14 counter stopped when core is halted
    14. 

  14. //   <o.26> DBG_TIM13_STOP           <i> TIM13 counter stopped when core is halted
    15. 

  15. //   <o.25> DBG_TIM12_STOP           <i> TIM12 counter stopped when core is halted
    16. 

  16. //   <o.21> DBG_CAN2_STOP            <i> Debug CAN2 stopped when core is halted
    17. 

  17. //   <o.20> DBG_TIM7_STOP            <i> TIM7 counter stopped when core is halted
    18. 

  18. //   <o.19> DBG_TIM6_STOP            <i> TIM6 counter stopped when core is halted
    19. 

  19. //   <o.18> DBG_TIM5_STOP            <i> TIM5 counter stopped when core is halted
    20. 

  20. //   <o.17> DBG_TIM8_STOP            <i> TIM8 counter stopped when core is halted
    21. 

  21. //   <o.16> DBG_I2C2_SMBUS_TIMEOUT   <i> SMBUS timeout mode stopped when core is halted
    22. 

  22. //   <o.15> DBG_I2C1_SMBUS_TIMEOUT   <i> SMBUS timeout mode stopped when core is halted
    23. 

  23. //   <o.14> DBG_CAN1_STOP            <i> Debug CAN1 stopped when Core is halted
    24. 

  24. //   <o.13> DBG_TIM4_STOP            <i> TIM4 counter stopped when core is halted
    25. 

  25. //   <o.12> DBG_TIM3_STOP            <i> TIM3 counter stopped when core is halted
    26. 

  26. //   <o.11> DBG_TIM2_STOP            <i> TIM2 counter stopped when core is halted
    27. 

  27. //   <o.10> DBG_TIM1_STOP            <i> TIM1 counter stopped when core is halted
    28. 

  28. //   <o.9>  DBG_WWDG_STOP            <i> Debug window watchdog stopped when core is halted
    29. 

  29. //   <o.8>  DBG_IWDG_STOP            <i> Debug independent watchdog stopped when core is halted
    30. 

  30. //   <o.2>  DBG_STANDBY              <i> Debug standby mode
    31. 

  31. //   <o.1>  DBG_STOP                 <i> Debug stop mode
    32. 

  32. //   <o.0>  DBG_SLEEP                <i> Debug sleep mode
    33. 

  33. // </h>
    34. 

  34. DbgMCU_CR = 0x00000007;
    35. 

  35. 

  36. // <<< end of configuration section >>>
    37.