core_sc000.h 45 KB

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  1. /**************************************************************************//**
  2. * @file core_sc000.h
  3. * @brief CMSIS SC000 Core Peripheral Access Layer Header File
  4. * @version V5.0.5
  5. * @date 28. May 2018
  6. ******************************************************************************/
  7. /*
  8. * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  9. *
  10. * SPDX-License-Identifier: Apache-2.0
  11. *
  12. * Licensed under the Apache License, Version 2.0 (the License); you may
  13. * not use this file except in compliance with the License.
  14. * You may obtain a copy of the License at
  15. *
  16. * www.apache.org/licenses/LICENSE-2.0
  17. *
  18. * Unless required by applicable law or agreed to in writing, software
  19. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21. * See the License for the specific language governing permissions and
  22. * limitations under the License.
  23. */
  24. #if defined ( __ICCARM__ )
  25. #pragma system_include /* treat file as system include file for MISRA check */
  26. #elif defined (__clang__)
  27. #pragma clang system_header /* treat file as system include file */
  28. #endif
  29. #ifndef __CORE_SC000_H_GENERIC
  30. #define __CORE_SC000_H_GENERIC
  31. #include <stdint.h>
  32. #ifdef __cplusplus
  33. extern "C" {
  34. #endif
  35. /**
  36. \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
  37. CMSIS violates the following MISRA-C:2004 rules:
  38. \li Required Rule 8.5, object/function definition in header file.<br>
  39. Function definitions in header files are used to allow 'inlining'.
  40. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
  41. Unions are used for effective representation of core registers.
  42. \li Advisory Rule 19.7, Function-like macro defined.<br>
  43. Function-like macros are used to allow more efficient code.
  44. */
  45. /*******************************************************************************
  46. * CMSIS definitions
  47. ******************************************************************************/
  48. /**
  49. \ingroup SC000
  50. @{
  51. */
  52. #include "cmsis_version.h"
  53. /* CMSIS SC000 definitions */
  54. #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
  55. #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
  56. #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
  57. __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
  58. #define __CORTEX_SC (000U) /*!< Cortex secure core */
  59. /** __FPU_USED indicates whether an FPU is used or not.
  60. This core does not support an FPU at all
  61. */
  62. #define __FPU_USED 0U
  63. #if defined ( __CC_ARM )
  64. #if defined __TARGET_FPU_VFP
  65. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  66. #endif
  67. #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  68. #if defined __ARM_PCS_VFP
  69. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  70. #endif
  71. #elif defined ( __GNUC__ )
  72. #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  73. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  74. #endif
  75. #elif defined ( __ICCARM__ )
  76. #if defined __ARMVFP__
  77. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  78. #endif
  79. #elif defined ( __TI_ARM__ )
  80. #if defined __TI_VFP_SUPPORT__
  81. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  82. #endif
  83. #elif defined ( __TASKING__ )
  84. #if defined __FPU_VFP__
  85. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  86. #endif
  87. #elif defined ( __CSMC__ )
  88. #if ( __CSMC__ & 0x400U)
  89. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  90. #endif
  91. #endif
  92. #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
  93. #ifdef __cplusplus
  94. }
  95. #endif
  96. #endif /* __CORE_SC000_H_GENERIC */
  97. #ifndef __CMSIS_GENERIC
  98. #ifndef __CORE_SC000_H_DEPENDANT
  99. #define __CORE_SC000_H_DEPENDANT
  100. #ifdef __cplusplus
  101. extern "C" {
  102. #endif
  103. /* check device defines and use defaults */
  104. #if defined __CHECK_DEVICE_DEFINES
  105. #ifndef __SC000_REV
  106. #define __SC000_REV 0x0000U
  107. #warning "__SC000_REV not defined in device header file; using default!"
  108. #endif
  109. #ifndef __MPU_PRESENT
  110. #define __MPU_PRESENT 0U
  111. #warning "__MPU_PRESENT not defined in device header file; using default!"
  112. #endif
  113. #ifndef __NVIC_PRIO_BITS
  114. #define __NVIC_PRIO_BITS 2U
  115. #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
  116. #endif
  117. #ifndef __Vendor_SysTickConfig
  118. #define __Vendor_SysTickConfig 0U
  119. #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
  120. #endif
  121. #endif
  122. /* IO definitions (access restrictions to peripheral registers) */
  123. /**
  124. \defgroup CMSIS_glob_defs CMSIS Global Defines
  125. <strong>IO Type Qualifiers</strong> are used
  126. \li to specify the access to peripheral variables.
  127. \li for automatic generation of peripheral register debug information.
  128. */
  129. #ifdef __cplusplus
  130. #define __I volatile /*!< Defines 'read only' permissions */
  131. #else
  132. #define __I volatile const /*!< Defines 'read only' permissions */
  133. #endif
  134. #define __O volatile /*!< Defines 'write only' permissions */
  135. #define __IO volatile /*!< Defines 'read / write' permissions */
  136. /* following defines should be used for structure members */
  137. #define __IM volatile const /*! Defines 'read only' structure member permissions */
  138. #define __OM volatile /*! Defines 'write only' structure member permissions */
  139. #define __IOM volatile /*! Defines 'read / write' structure member permissions */
  140. /*@} end of group SC000 */
  141. /*******************************************************************************
  142. * Register Abstraction
  143. Core Register contain:
  144. - Core Register
  145. - Core NVIC Register
  146. - Core SCB Register
  147. - Core SysTick Register
  148. - Core MPU Register
  149. ******************************************************************************/
  150. /**
  151. \defgroup CMSIS_core_register Defines and Type Definitions
  152. \brief Type definitions and defines for Cortex-M processor based devices.
  153. */
  154. /**
  155. \ingroup CMSIS_core_register
  156. \defgroup CMSIS_CORE Status and Control Registers
  157. \brief Core Register type definitions.
  158. @{
  159. */
  160. /**
  161. \brief Union type to access the Application Program Status Register (APSR).
  162. */
  163. typedef union
  164. {
  165. struct
  166. {
  167. uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
  168. uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
  169. uint32_t C:1; /*!< bit: 29 Carry condition code flag */
  170. uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
  171. uint32_t N:1; /*!< bit: 31 Negative condition code flag */
  172. } b; /*!< Structure used for bit access */
  173. uint32_t w; /*!< Type used for word access */
  174. } APSR_Type;
  175. /* APSR Register Definitions */
  176. #define APSR_N_Pos 31U /*!< APSR: N Position */
  177. #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
  178. #define APSR_Z_Pos 30U /*!< APSR: Z Position */
  179. #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
  180. #define APSR_C_Pos 29U /*!< APSR: C Position */
  181. #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
  182. #define APSR_V_Pos 28U /*!< APSR: V Position */
  183. #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
  184. /**
  185. \brief Union type to access the Interrupt Program Status Register (IPSR).
  186. */
  187. typedef union
  188. {
  189. struct
  190. {
  191. uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
  192. uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
  193. } b; /*!< Structure used for bit access */
  194. uint32_t w; /*!< Type used for word access */
  195. } IPSR_Type;
  196. /* IPSR Register Definitions */
  197. #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
  198. #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
  199. /**
  200. \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
  201. */
  202. typedef union
  203. {
  204. struct
  205. {
  206. uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
  207. uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
  208. uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
  209. uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
  210. uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
  211. uint32_t C:1; /*!< bit: 29 Carry condition code flag */
  212. uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
  213. uint32_t N:1; /*!< bit: 31 Negative condition code flag */
  214. } b; /*!< Structure used for bit access */
  215. uint32_t w; /*!< Type used for word access */
  216. } xPSR_Type;
  217. /* xPSR Register Definitions */
  218. #define xPSR_N_Pos 31U /*!< xPSR: N Position */
  219. #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
  220. #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
  221. #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
  222. #define xPSR_C_Pos 29U /*!< xPSR: C Position */
  223. #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
  224. #define xPSR_V_Pos 28U /*!< xPSR: V Position */
  225. #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
  226. #define xPSR_T_Pos 24U /*!< xPSR: T Position */
  227. #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
  228. #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
  229. #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
  230. /**
  231. \brief Union type to access the Control Registers (CONTROL).
  232. */
  233. typedef union
  234. {
  235. struct
  236. {
  237. uint32_t _reserved0:1; /*!< bit: 0 Reserved */
  238. uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
  239. uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
  240. } b; /*!< Structure used for bit access */
  241. uint32_t w; /*!< Type used for word access */
  242. } CONTROL_Type;
  243. /* CONTROL Register Definitions */
  244. #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
  245. #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
  246. /*@} end of group CMSIS_CORE */
  247. /**
  248. \ingroup CMSIS_core_register
  249. \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
  250. \brief Type definitions for the NVIC Registers
  251. @{
  252. */
  253. /**
  254. \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  255. */
  256. typedef struct
  257. {
  258. __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
  259. uint32_t RESERVED0[31U];
  260. __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
  261. uint32_t RSERVED1[31U];
  262. __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
  263. uint32_t RESERVED2[31U];
  264. __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
  265. uint32_t RESERVED3[31U];
  266. uint32_t RESERVED4[64U];
  267. __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
  268. } NVIC_Type;
  269. /*@} end of group CMSIS_NVIC */
  270. /**
  271. \ingroup CMSIS_core_register
  272. \defgroup CMSIS_SCB System Control Block (SCB)
  273. \brief Type definitions for the System Control Block Registers
  274. @{
  275. */
  276. /**
  277. \brief Structure type to access the System Control Block (SCB).
  278. */
  279. typedef struct
  280. {
  281. __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
  282. __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
  283. __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
  284. __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
  285. __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
  286. __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
  287. uint32_t RESERVED0[1U];
  288. __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
  289. __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
  290. uint32_t RESERVED1[154U];
  291. __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
  292. } SCB_Type;
  293. /* SCB CPUID Register Definitions */
  294. #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
  295. #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
  296. #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
  297. #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
  298. #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
  299. #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
  300. #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
  301. #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
  302. #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
  303. #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
  304. /* SCB Interrupt Control State Register Definitions */
  305. #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
  306. #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
  307. #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
  308. #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
  309. #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
  310. #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
  311. #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
  312. #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
  313. #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
  314. #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
  315. #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
  316. #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
  317. #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
  318. #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
  319. #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
  320. #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
  321. #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
  322. #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
  323. /* SCB Interrupt Control State Register Definitions */
  324. #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
  325. #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
  326. /* SCB Application Interrupt and Reset Control Register Definitions */
  327. #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
  328. #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
  329. #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
  330. #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
  331. #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
  332. #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
  333. #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
  334. #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
  335. #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
  336. #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
  337. /* SCB System Control Register Definitions */
  338. #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
  339. #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
  340. #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
  341. #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
  342. #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
  343. #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
  344. /* SCB Configuration Control Register Definitions */
  345. #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
  346. #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
  347. #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
  348. #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
  349. /* SCB System Handler Control and State Register Definitions */
  350. #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
  351. #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
  352. /*@} end of group CMSIS_SCB */
  353. /**
  354. \ingroup CMSIS_core_register
  355. \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
  356. \brief Type definitions for the System Control and ID Register not in the SCB
  357. @{
  358. */
  359. /**
  360. \brief Structure type to access the System Control and ID Register not in the SCB.
  361. */
  362. typedef struct
  363. {
  364. uint32_t RESERVED0[2U];
  365. __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
  366. } SCnSCB_Type;
  367. /* Auxiliary Control Register Definitions */
  368. #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
  369. #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
  370. /*@} end of group CMSIS_SCnotSCB */
  371. /**
  372. \ingroup CMSIS_core_register
  373. \defgroup CMSIS_SysTick System Tick Timer (SysTick)
  374. \brief Type definitions for the System Timer Registers.
  375. @{
  376. */
  377. /**
  378. \brief Structure type to access the System Timer (SysTick).
  379. */
  380. typedef struct
  381. {
  382. __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
  383. __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
  384. __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
  385. __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
  386. } SysTick_Type;
  387. /* SysTick Control / Status Register Definitions */
  388. #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
  389. #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
  390. #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
  391. #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
  392. #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
  393. #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
  394. #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
  395. #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
  396. /* SysTick Reload Register Definitions */
  397. #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
  398. #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
  399. /* SysTick Current Register Definitions */
  400. #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
  401. #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
  402. /* SysTick Calibration Register Definitions */
  403. #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
  404. #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
  405. #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
  406. #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
  407. #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
  408. #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
  409. /*@} end of group CMSIS_SysTick */
  410. #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
  411. /**
  412. \ingroup CMSIS_core_register
  413. \defgroup CMSIS_MPU Memory Protection Unit (MPU)
  414. \brief Type definitions for the Memory Protection Unit (MPU)
  415. @{
  416. */
  417. /**
  418. \brief Structure type to access the Memory Protection Unit (MPU).
  419. */
  420. typedef struct
  421. {
  422. __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
  423. __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
  424. __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
  425. __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
  426. __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
  427. } MPU_Type;
  428. /* MPU Type Register Definitions */
  429. #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
  430. #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
  431. #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
  432. #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
  433. #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
  434. #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
  435. /* MPU Control Register Definitions */
  436. #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
  437. #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
  438. #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
  439. #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
  440. #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
  441. #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
  442. /* MPU Region Number Register Definitions */
  443. #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
  444. #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
  445. /* MPU Region Base Address Register Definitions */
  446. #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
  447. #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
  448. #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
  449. #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
  450. #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
  451. #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
  452. /* MPU Region Attribute and Size Register Definitions */
  453. #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
  454. #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
  455. #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
  456. #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
  457. #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
  458. #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
  459. #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
  460. #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
  461. #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
  462. #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
  463. #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
  464. #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
  465. #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
  466. #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
  467. #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
  468. #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
  469. #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
  470. #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
  471. #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
  472. #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
  473. /*@} end of group CMSIS_MPU */
  474. #endif
  475. /**
  476. \ingroup CMSIS_core_register
  477. \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
  478. \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
  479. Therefore they are not covered by the SC000 header file.
  480. @{
  481. */
  482. /*@} end of group CMSIS_CoreDebug */
  483. /**
  484. \ingroup CMSIS_core_register
  485. \defgroup CMSIS_core_bitfield Core register bit field macros
  486. \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
  487. @{
  488. */
  489. /**
  490. \brief Mask and shift a bit field value for use in a register bit range.
  491. \param[in] field Name of the register bit field.
  492. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
  493. \return Masked and shifted value.
  494. */
  495. #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
  496. /**
  497. \brief Mask and shift a register value to extract a bit filed value.
  498. \param[in] field Name of the register bit field.
  499. \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
  500. \return Masked and shifted bit field value.
  501. */
  502. #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
  503. /*@} end of group CMSIS_core_bitfield */
  504. /**
  505. \ingroup CMSIS_core_register
  506. \defgroup CMSIS_core_base Core Definitions
  507. \brief Definitions for base addresses, unions, and structures.
  508. @{
  509. */
  510. /* Memory mapping of Core Hardware */
  511. #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
  512. #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
  513. #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
  514. #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
  515. #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
  516. #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
  517. #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
  518. #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
  519. #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
  520. #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
  521. #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
  522. #endif
  523. /*@} */
  524. /*******************************************************************************
  525. * Hardware Abstraction Layer
  526. Core Function Interface contains:
  527. - Core NVIC Functions
  528. - Core SysTick Functions
  529. - Core Register Access Functions
  530. ******************************************************************************/
  531. /**
  532. \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
  533. */
  534. /* ########################## NVIC functions #################################### */
  535. /**
  536. \ingroup CMSIS_Core_FunctionInterface
  537. \defgroup CMSIS_Core_NVICFunctions NVIC Functions
  538. \brief Functions that manage interrupts and exceptions via the NVIC.
  539. @{
  540. */
  541. #ifdef CMSIS_NVIC_VIRTUAL
  542. #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
  543. #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
  544. #endif
  545. #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
  546. #else
  547. /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
  548. /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
  549. #define NVIC_EnableIRQ __NVIC_EnableIRQ
  550. #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
  551. #define NVIC_DisableIRQ __NVIC_DisableIRQ
  552. #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
  553. #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
  554. #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
  555. /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
  556. #define NVIC_SetPriority __NVIC_SetPriority
  557. #define NVIC_GetPriority __NVIC_GetPriority
  558. #define NVIC_SystemReset __NVIC_SystemReset
  559. #endif /* CMSIS_NVIC_VIRTUAL */
  560. #ifdef CMSIS_VECTAB_VIRTUAL
  561. #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
  562. #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
  563. #endif
  564. #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
  565. #else
  566. #define NVIC_SetVector __NVIC_SetVector
  567. #define NVIC_GetVector __NVIC_GetVector
  568. #endif /* (CMSIS_VECTAB_VIRTUAL) */
  569. #define NVIC_USER_IRQ_OFFSET 16
  570. /* The following EXC_RETURN values are saved the LR on exception entry */
  571. #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
  572. #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
  573. #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
  574. /* Interrupt Priorities are WORD accessible only under Armv6-M */
  575. /* The following MACROS handle generation of the register offset and byte masks */
  576. #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
  577. #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
  578. #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
  579. /**
  580. \brief Enable Interrupt
  581. \details Enables a device specific interrupt in the NVIC interrupt controller.
  582. \param [in] IRQn Device specific interrupt number.
  583. \note IRQn must not be negative.
  584. */
  585. __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
  586. {
  587. if ((int32_t)(IRQn) >= 0)
  588. {
  589. NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  590. }
  591. }
  592. /**
  593. \brief Get Interrupt Enable status
  594. \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
  595. \param [in] IRQn Device specific interrupt number.
  596. \return 0 Interrupt is not enabled.
  597. \return 1 Interrupt is enabled.
  598. \note IRQn must not be negative.
  599. */
  600. __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
  601. {
  602. if ((int32_t)(IRQn) >= 0)
  603. {
  604. return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  605. }
  606. else
  607. {
  608. return(0U);
  609. }
  610. }
  611. /**
  612. \brief Disable Interrupt
  613. \details Disables a device specific interrupt in the NVIC interrupt controller.
  614. \param [in] IRQn Device specific interrupt number.
  615. \note IRQn must not be negative.
  616. */
  617. __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
  618. {
  619. if ((int32_t)(IRQn) >= 0)
  620. {
  621. NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  622. __DSB();
  623. __ISB();
  624. }
  625. }
  626. /**
  627. \brief Get Pending Interrupt
  628. \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
  629. \param [in] IRQn Device specific interrupt number.
  630. \return 0 Interrupt status is not pending.
  631. \return 1 Interrupt status is pending.
  632. \note IRQn must not be negative.
  633. */
  634. __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
  635. {
  636. if ((int32_t)(IRQn) >= 0)
  637. {
  638. return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  639. }
  640. else
  641. {
  642. return(0U);
  643. }
  644. }
  645. /**
  646. \brief Set Pending Interrupt
  647. \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
  648. \param [in] IRQn Device specific interrupt number.
  649. \note IRQn must not be negative.
  650. */
  651. __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
  652. {
  653. if ((int32_t)(IRQn) >= 0)
  654. {
  655. NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  656. }
  657. }
  658. /**
  659. \brief Clear Pending Interrupt
  660. \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
  661. \param [in] IRQn Device specific interrupt number.
  662. \note IRQn must not be negative.
  663. */
  664. __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  665. {
  666. if ((int32_t)(IRQn) >= 0)
  667. {
  668. NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  669. }
  670. }
  671. /**
  672. \brief Set Interrupt Priority
  673. \details Sets the priority of a device specific interrupt or a processor exception.
  674. The interrupt number can be positive to specify a device specific interrupt,
  675. or negative to specify a processor exception.
  676. \param [in] IRQn Interrupt number.
  677. \param [in] priority Priority to set.
  678. \note The priority cannot be set for every processor exception.
  679. */
  680. __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
  681. {
  682. if ((int32_t)(IRQn) >= 0)
  683. {
  684. NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
  685. (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  686. }
  687. else
  688. {
  689. SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
  690. (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  691. }
  692. }
  693. /**
  694. \brief Get Interrupt Priority
  695. \details Reads the priority of a device specific interrupt or a processor exception.
  696. The interrupt number can be positive to specify a device specific interrupt,
  697. or negative to specify a processor exception.
  698. \param [in] IRQn Interrupt number.
  699. \return Interrupt Priority.
  700. Value is aligned automatically to the implemented priority bits of the microcontroller.
  701. */
  702. __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
  703. {
  704. if ((int32_t)(IRQn) >= 0)
  705. {
  706. return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  707. }
  708. else
  709. {
  710. return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  711. }
  712. }
  713. /**
  714. \brief Set Interrupt Vector
  715. \details Sets an interrupt vector in SRAM based interrupt vector table.
  716. The interrupt number can be positive to specify a device specific interrupt,
  717. or negative to specify a processor exception.
  718. VTOR must been relocated to SRAM before.
  719. \param [in] IRQn Interrupt number
  720. \param [in] vector Address of interrupt handler function
  721. */
  722. __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
  723. {
  724. uint32_t *vectors = (uint32_t *)SCB->VTOR;
  725. vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
  726. }
  727. /**
  728. \brief Get Interrupt Vector
  729. \details Reads an interrupt vector from interrupt vector table.
  730. The interrupt number can be positive to specify a device specific interrupt,
  731. or negative to specify a processor exception.
  732. \param [in] IRQn Interrupt number.
  733. \return Address of interrupt handler function
  734. */
  735. __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
  736. {
  737. uint32_t *vectors = (uint32_t *)SCB->VTOR;
  738. return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
  739. }
  740. /**
  741. \brief System Reset
  742. \details Initiates a system reset request to reset the MCU.
  743. */
  744. __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
  745. {
  746. __DSB(); /* Ensure all outstanding memory accesses included
  747. buffered write are completed before reset */
  748. SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  749. SCB_AIRCR_SYSRESETREQ_Msk);
  750. __DSB(); /* Ensure completion of memory access */
  751. for(;;) /* wait until reset */
  752. {
  753. __NOP();
  754. }
  755. }
  756. /*@} end of CMSIS_Core_NVICFunctions */
  757. /* ########################## FPU functions #################################### */
  758. /**
  759. \ingroup CMSIS_Core_FunctionInterface
  760. \defgroup CMSIS_Core_FpuFunctions FPU Functions
  761. \brief Function that provides FPU type.
  762. @{
  763. */
  764. /**
  765. \brief get FPU type
  766. \details returns the FPU type
  767. \returns
  768. - \b 0: No FPU
  769. - \b 1: Single precision FPU
  770. - \b 2: Double + Single precision FPU
  771. */
  772. __STATIC_INLINE uint32_t SCB_GetFPUType(void)
  773. {
  774. return 0U; /* No FPU */
  775. }
  776. /*@} end of CMSIS_Core_FpuFunctions */
  777. /* ################################## SysTick function ############################################ */
  778. /**
  779. \ingroup CMSIS_Core_FunctionInterface
  780. \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
  781. \brief Functions that configure the System.
  782. @{
  783. */
  784. #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
  785. /**
  786. \brief System Tick Configuration
  787. \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
  788. Counter is in free running mode to generate periodic interrupts.
  789. \param [in] ticks Number of ticks between two interrupts.
  790. \return 0 Function succeeded.
  791. \return 1 Function failed.
  792. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
  793. function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
  794. must contain a vendor-specific implementation of this function.
  795. */
  796. __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
  797. {
  798. if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
  799. {
  800. return (1UL); /* Reload value impossible */
  801. }
  802. SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
  803. NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  804. SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
  805. SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
  806. SysTick_CTRL_TICKINT_Msk |
  807. SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
  808. return (0UL); /* Function successful */
  809. }
  810. #endif
  811. /*@} end of CMSIS_Core_SysTickFunctions */
  812. #ifdef __cplusplus
  813. }
  814. #endif
  815. #endif /* __CORE_SC000_H_DEPENDANT */
  816. #endif /* __CMSIS_GENERIC */