mpu_armv7.h 11 KB

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  1. /******************************************************************************
  2. * @file mpu_armv7.h
  3. * @brief CMSIS MPU API for Armv7-M MPU
  4. * @version V5.0.4
  5. * @date 10. January 2018
  6. ******************************************************************************/
  7. /*
  8. * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
  9. *
  10. * SPDX-License-Identifier: Apache-2.0
  11. *
  12. * Licensed under the Apache License, Version 2.0 (the License); you may
  13. * not use this file except in compliance with the License.
  14. * You may obtain a copy of the License at
  15. *
  16. * www.apache.org/licenses/LICENSE-2.0
  17. *
  18. * Unless required by applicable law or agreed to in writing, software
  19. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21. * See the License for the specific language governing permissions and
  22. * limitations under the License.
  23. */
  24. #if defined ( __ICCARM__ )
  25. #pragma system_include /* treat file as system include file for MISRA check */
  26. #elif defined (__clang__)
  27. #pragma clang system_header /* treat file as system include file */
  28. #endif
  29. #ifndef ARM_MPU_ARMV7_H
  30. #define ARM_MPU_ARMV7_H
  31. #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
  32. #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
  33. #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
  34. #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
  35. #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
  36. #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
  37. #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
  38. #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
  39. #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
  40. #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
  41. #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
  42. #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
  43. #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
  44. #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
  45. #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
  46. #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
  47. #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
  48. #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
  49. #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
  50. #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
  51. #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
  52. #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
  53. #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
  54. #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
  55. #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
  56. #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
  57. #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
  58. #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
  59. #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
  60. #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
  61. #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
  62. #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
  63. #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
  64. #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
  65. /** MPU Region Base Address Register Value
  66. *
  67. * \param Region The region to be configured, number 0 to 15.
  68. * \param BaseAddress The base address for the region.
  69. */
  70. #define ARM_MPU_RBAR(Region, BaseAddress) \
  71. (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
  72. ((Region) & MPU_RBAR_REGION_Msk) | \
  73. (MPU_RBAR_VALID_Msk))
  74. /**
  75. * MPU Memory Access Attributes
  76. *
  77. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
  78. * \param IsShareable Region is shareable between multiple bus masters.
  79. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
  80. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
  81. */
  82. #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
  83. ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
  84. (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
  85. (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
  86. (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
  87. /**
  88. * MPU Region Attribute and Size Register Value
  89. *
  90. * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
  91. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
  92. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
  93. * \param SubRegionDisable Sub-region disable field.
  94. * \param Size Region size of the region to be configured, for example 4K, 8K.
  95. */
  96. #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
  97. ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
  98. (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
  99. (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
  100. /**
  101. * MPU Region Attribute and Size Register Value
  102. *
  103. * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
  104. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
  105. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
  106. * \param IsShareable Region is shareable between multiple bus masters.
  107. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
  108. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
  109. * \param SubRegionDisable Sub-region disable field.
  110. * \param Size Region size of the region to be configured, for example 4K, 8K.
  111. */
  112. #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
  113. ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
  114. /**
  115. * MPU Memory Access Attribute for strongly ordered memory.
  116. * - TEX: 000b
  117. * - Shareable
  118. * - Non-cacheable
  119. * - Non-bufferable
  120. */
  121. #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
  122. /**
  123. * MPU Memory Access Attribute for device memory.
  124. * - TEX: 000b (if non-shareable) or 010b (if shareable)
  125. * - Shareable or non-shareable
  126. * - Non-cacheable
  127. * - Bufferable (if shareable) or non-bufferable (if non-shareable)
  128. *
  129. * \param IsShareable Configures the device memory as shareable or non-shareable.
  130. */
  131. #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
  132. /**
  133. * MPU Memory Access Attribute for normal memory.
  134. * - TEX: 1BBb (reflecting outer cacheability rules)
  135. * - Shareable or non-shareable
  136. * - Cacheable or non-cacheable (reflecting inner cacheability rules)
  137. * - Bufferable or non-bufferable (reflecting inner cacheability rules)
  138. *
  139. * \param OuterCp Configures the outer cache policy.
  140. * \param InnerCp Configures the inner cache policy.
  141. * \param IsShareable Configures the memory as shareable or non-shareable.
  142. */
  143. #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
  144. /**
  145. * MPU Memory Access Attribute non-cacheable policy.
  146. */
  147. #define ARM_MPU_CACHEP_NOCACHE 0U
  148. /**
  149. * MPU Memory Access Attribute write-back, write and read allocate policy.
  150. */
  151. #define ARM_MPU_CACHEP_WB_WRA 1U
  152. /**
  153. * MPU Memory Access Attribute write-through, no write allocate policy.
  154. */
  155. #define ARM_MPU_CACHEP_WT_NWA 2U
  156. /**
  157. * MPU Memory Access Attribute write-back, no write allocate policy.
  158. */
  159. #define ARM_MPU_CACHEP_WB_NWA 3U
  160. /**
  161. * Struct for a single MPU Region
  162. */
  163. typedef struct {
  164. uint32_t RBAR; //!< The region base address register value (RBAR)
  165. uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
  166. } ARM_MPU_Region_t;
  167. /** Enable the MPU.
  168. * \param MPU_Control Default access permissions for unconfigured regions.
  169. */
  170. __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
  171. {
  172. __DSB();
  173. __ISB();
  174. MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
  175. #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  176. SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
  177. #endif
  178. }
  179. /** Disable the MPU.
  180. */
  181. __STATIC_INLINE void ARM_MPU_Disable(void)
  182. {
  183. __DSB();
  184. __ISB();
  185. #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  186. SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
  187. #endif
  188. MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
  189. }
  190. /** Clear and disable the given MPU region.
  191. * \param rnr Region number to be cleared.
  192. */
  193. __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
  194. {
  195. MPU->RNR = rnr;
  196. MPU->RASR = 0U;
  197. }
  198. /** Configure an MPU region.
  199. * \param rbar Value for RBAR register.
  200. * \param rsar Value for RSAR register.
  201. */
  202. __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
  203. {
  204. MPU->RBAR = rbar;
  205. MPU->RASR = rasr;
  206. }
  207. /** Configure the given MPU region.
  208. * \param rnr Region number to be configured.
  209. * \param rbar Value for RBAR register.
  210. * \param rsar Value for RSAR register.
  211. */
  212. __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
  213. {
  214. MPU->RNR = rnr;
  215. MPU->RBAR = rbar;
  216. MPU->RASR = rasr;
  217. }
  218. /** Memcopy with strictly ordered memory access, e.g. for register targets.
  219. * \param dst Destination data is copied to.
  220. * \param src Source data is copied from.
  221. * \param len Amount of data words to be copied.
  222. */
  223. __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
  224. {
  225. uint32_t i;
  226. for (i = 0U; i < len; ++i)
  227. {
  228. dst[i] = src[i];
  229. }
  230. }
  231. /** Load the given number of MPU regions from a table.
  232. * \param table Pointer to the MPU configuration table.
  233. * \param cnt Amount of regions to be configured.
  234. */
  235. __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
  236. {
  237. const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
  238. while (cnt > MPU_TYPE_RALIASES) {
  239. orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
  240. table += MPU_TYPE_RALIASES;
  241. cnt -= MPU_TYPE_RALIASES;
  242. }
  243. orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
  244. }
  245. #endif